Computer systems and other electronic systems typically use buses for interconnecting integrated circuit components so that the components may communicate with one another. The buses frequently connect a master, such as a microprocessor or controller, to slaves, such as memories and bus transceivers. Generally, a master may send data to and receive data from one or more slaves. A slave may send data to and receive data from a master, but not another slave.
Each master and slave coupled to a prior bus typically includes output driver circuitry for driving signals onto the bus. Some prior bus systems have output drivers that user transistor-transistor logic (“TTL”) circuitry. Other prior bus systems have output drivers that include emitter-coupled logic (“ECL”) circuitry. Other output drivers use complementary metal-oxide-semiconductor (“CMOS”) circuitry or N-channel metal-oxide-semiconductor (“NMOS”) circuitry.
While many prior buses were driven by voltage level signals, it has become advantageous to provide buses that are driven by a current mode output driver. A benefit associated with a current mode driver is a reduction of peak switching current. In particular, the current mode driver draws a known current regardless of load and operating conditions. A further benefit is that the current mode driver typically supresses noise coupled from power and ground supplies.
A known current mode driver is shown in U.S. Pat. No. 5,254,883 (the “'883 patent”), which is assigned to the assignee of the present invention and incorporated herein by reference. The '883 patent discusses an apparatus and method for setting and maintaining the operating current of a current mode driver. The driver in the '883 patent includes an output transistor array, output logic circuitry coupled to the transistor array and a current controller coupled to the output logic circuitry.
For one embodiment, the current controller in the '883 patent is a resistor reference current controller. The current controller receives two input voltages, VTERM and VREF, the latter of which is applied to an input of a comparator. VTERM is coupled by a resistor to a node, which is in turn coupled to a second input of the comparator. The voltage at the node is controlled by a transistor array, which is in turn controlled in accordance with an output of the comparator.
When the transistor array is placed in the “off” state, i.e. there is no current flowing through the transistors of the array to ground, the voltage at the node is equal to VTERM. In addition, by using the output of the comparator to adjustably activate the transistor array, the '883 patent shows that the voltage at the node may be driven to be approximately equal to the reference voltage, VREF.
Knowing the value of VREF and VTERM, the current mode driver of the '833 patent therefore provides a binary signaling scheme utilizing a symmetrical voltage swing about VREF. Specifically, in a first current state (the “off” state), the current mode driver is not sinking current and the signal line (or bus line) is at a voltage, Vo=VTERM, representing a logic “0”. In a second current state (the “on” state), the current mode driver is sinking current to drive the voltage on the signal line (or bus line) to be:Vo=VTERM−2(VTERM−VREF).The second state therefore representing a logical “1.”
While the above techniques have met with substantial success, end users of data processing systems, such as computers, continue to demand increased throughput. Whether throughput is expressed in terms of bandwidth, processing speed or any other measure, the bottom line is the desire to get a block of data from point A to point B faster. At the same time, however, it is desirable to achieve such increases without requiring deviation from known semiconductor fabrication techniques.